This invention relates to circuitry for handling communication of digital information to which bits are added periodically for synchronization or the like, and more particularly to an interface having reduced area as compared to previously known such interfaces.
A communication protocol that is increasingly of interest is known as “64b/66b encoding.” This is a protocol in which 64 bits of data are scrambled (e.g., to achieve balance between the number of binary ones and the numbers of binary zeros that need to be transmitted so that there is no net direct current in the transmission) and two additional bits having one or more particular sequences are transmitted with each 64 bits as synchronization information. Thus for every 64 bits of information that need to be sent, 64 information bits and two SYNC bits are transmitted. The SYNC bits may be the sequence “10” or “01”. Extra bits of this kind may sometimes be referred to herein as “padding.” At the receiver end, the encoded “padded” data are decoded to remove the padding bits.
Serial communication of padded information can be a challenge because of possibly complicated clocking issues. For example, 66 bits of information may need to be transmitted in the time in which the data source produces 64 bits of real data. Similarly, the receiver circuitry needs to receive 66 bits in the time in which it will subsequently pass on the 64 bits of real data in that 66-bit transmission.
Circuitry for solving this problem, and allowing the different data widths to operate at different rates, so that the total number of bits transferred during a single clock cycle matches, is known, and is commonly referred to informally as a “gearbox.”
Thus, at the transmitter end, the data—e.g., 64 bits, are encoded to add in the two padding bits. The padded—e.g., 66-bit—groupings are then passed through a transmitter gearbox, where the larger number of padded bits used for processing—e.g., 66 bits—must be converted to the smaller number of bits—e.g., 64 bits (generally a power of 2 to be compatible with standard serializer-deserializers)—for transmission.
At the receiver end, the smaller—e.g., 64-bit—groupings of transmitted padded data are run through a receiver gearbox, where the smaller, but still padded, number of bits used for transmission—e.g., 64 bits—must be converted to the true, larger number—e.g., 66 bits—of padded data, which then can be decoded to remove the padding bits and restore the original unpadded—e.g., 64-bit—data.
In accordance with IEEE Standard 802.3ae-2002, published Aug. 30, 2002, such decoding at the receiver has heretofore been performed under control of a state machine set forth in that standard. That state machine requires knowledge of a current sample to be decoded, as well as the two following samples. Accordingly, a receiver for such a padded protocol—e.g., 64b/66b encoding—has heretofore had to include buffering for two samples, each of which is 66 bits wide.
It would be desirable to be able to provide such receiver decoding circuitry with reduced buffering requirements, so that the chip area occupied by such a receiver could be reduced.